Wide bandgap semiconductors have been used extensively in various kinds of semiconductor devices including power elements (which will also be referred to herein as “power devices”), hostile-environment elements, high temperature operating elements, and radio frequency elements. In particular, application of such a material to power devices such as switching elements and rectifier elements has attracted a lot of attention.
Among those wide bandgap semiconductors, power devices that use silicon carbide (SiC) (which are also called “SiC power devices”) have been developed particularly extensively because a SiC substrate can be made relatively easily and because silicon dioxide (SiO2) can be obtained as a gate insulating film of quality by thermally oxidizing SiC.
Field effect transistors including a metal-insulator-semiconductor field effect transistor (MISFET) and a metal semiconductor field effect transistor (MESFET) are typical switching elements among various power devices that use SiC. Such a switching element can switch between ON state in which drain current of several amperes (A) or more flows and OFF state in which the drain current becomes zero by changing the voltages applied to between its gate and source electrodes. Also, in the OFF state, SiC will achieve as high a breakdown voltage as several hundred volts or more.
SiC has a higher dielectric breakdown voltage and a higher thermal conductivity than Si. That is why a power device that uses SiC (which will be referred to herein as a “SiC power device”) can have a higher dielectric strength and will cause smaller loss than a Si power device. As a result, a SiC power device can operate at a higher temperature, under a higher voltage applied, and with a larger amount of current supplied, than a Si power device.
To make an even larger amount of current flow through a power device such as a MISFET, it is effective to increase the channel density. For that reason, a vertical power MISFET with a trench gate structure has been proposed as a replacement for a conventional planar gate structure. In the planar gate structure, a channel region is defined on the surface of a semiconductor layer. In the trench gate structure, on the other hand, a channel region is defined on the side surface of a trench that has been cut through a semiconductor layer (see Patent Document No. 3, for example).
Hereinafter, a cross-sectional structure of a vertical MISFET with the trench gate structure will be described with reference to the accompanying drawings. The vertical MISFET ordinarily has a plurality of unit cells that are arranged two-dimensionally. Each of those unit cells has a trench gate.
FIG. 5 is a cross-sectional view illustrating one cell pitch (i.e., a single unit cell) of a known vertical MISFET with the trench gate structure. In the example illustrated in FIG. 5, each unit cell has a trench gate, of which a side surface is substantially perpendicular to the principal surface of the substrate.
The vertical MISFET shown in FIG. 5 includes a substrate 1 of silicon carbide and a silicon carbide layer 2 that has been formed on the principal surface of the substrate 1. The silicon carbide layer 2 includes an n-type drift region 2d that has been defined on the principal surface of the substrate 1 and a p-type body region 3 that has been defined on the drift region 2d. An n-type source region 4 forms part of the surface region of the body region 3. A trench 5 is formed in the silicon carbide layer 2 so as to run through the body region 3 and reach the drift region 2d. In this example, the trench 5 has a side surface that is perpendicular to the principal surface of the substrate 1. Inside of the trench 5, arranged are a gate electrode 7 and a gate insulating film 6 that insulates the gate electrode 7 from the silicon carbide layer 2. Further arranged on the silicon carbide layer 2 is a source electrode 8 that contacts with the source region 4. And a drain electrode 9 is arranged on the back surface of the substrate 1.
A vertical MISFET like this may be fabricated in the following manner.
First of all, on the principal surface of an n-type substrate 1 with low resistivity, formed is a silicon carbide layer 2 having the same crystal structure as the substrate 1. For example, an n-type drift region 2d and a p-type body region 3 are defined in this order by epitaxial growth process on the principal surface of the substrate 1, thereby obtaining a silicon carbide layer 2. After that, a mask layer (not shown) of silicon dioxide is put on a predetermined area of the silicon carbide layer 2 and used as a mask through which n-type dopant ions (such as N (nitrogen) ions) are implanted into the body region 3, thereby defining a source region 4 in the body region 3.
After the mask has been removed, an Al film (not shown) is deposited on a part of the source region 4 with an oxide film interposed between them, and used as a mask, through which a trench 5 is cut to reach the drift region 2d. 
Next, a gate insulating film 6 and a gate electrode 7 are formed in this order inside of the trench 5. The gate insulating film 6 may be an oxide film, which is obtained by thermally oxidizing the silicon carbide layer 2.
The gate electrode 7 may be formed by depositing polysilicon on the gate insulating film 6 by low pressure chemical vapor deposition (LP-CVD) process and then patterning it, for example. Meanwhile, a source electrode 8 is formed on the silicon carbide layer 2 to cover both the body region 3 and the source region 4, while a drain electrode 9 is formed on the back surface of the substrate 1. In this manner, a vertical MISFET with a trench gate structure is completed.
In a MISFET with such a trench gate structure, when the source electrode 8 and the gate electrode 7 are both grounded or when a negative bias voltage is applied to the gate electrode 7, holes are accumulated in the vicinity of the interface between the body region 3 and the gate insulating film 6 in the region between the source region 4 and the drift region 2d, and the path of electrons which are conduction carriers is cut off. As a result, no current flows (i.e., the MISFET turns OFF). In this case, if a high voltage is applied to between the drain electrode 9 and the source electrode 8 so that the drain electrode 9 has positive potential, then the pn junction between the body region 3 and the drift region 2d becomes reverse biased. As a result, a depletion layer expands in the body region 3 and in the drift region 2d and a high voltage can be maintained.
On the other hand, if a positive bias voltage that is equal to or higher than a threshold voltage is applied to the gate electrode 7, electrons are induced and inverted in the vicinity of the interface between the body region 3 and the gate insulating film 6 in the region between the source region 4 and the drift region 2d, and an inversion layer is formed there. As a result, carriers flow from the source electrode 8 toward the drain electrode 9 by way of the source region 4, the inversion layer (not shown) that that has been formed in the body region 3 and that contacts with the gate insulating film 6, the drift region 2d and the substrate 1. That is to say, the MISFET turns ON.
In a vertical MISFET with the planar structure, a junction field effect transistor (which will be abbreviated herein as “JFET”) is formed as a parasitic transistor between adjacent unit cells and produces a resistive component (JFET resistance). This JFET resistance is produced when current flows through the drift region 2d that is interposed between adjacent body regions 3. The narrower the interval between those unit cells (i.e., the narrower the gap between the adjacent body regions 3), the greater the JFET resistance. That is why if the cell pitch is reduced to cut down the size, the ON-state resistance increases as the JFET resistance rises.
On the other hand, since the MISFET with the trench gate structure has no JFET resistance, the ON-state resistance decreases monotonically as the cell pitch is reduced, which is beneficial. For that reason, to cut down the size of a unit cell, it is more advantageous to adopt a MISFET with the trench gate structure.
In a MISFET with the trench gate structure, however, the intensity of the electric field applied to the gate insulating film 6 becomes very high, which is a problem. Hereinafter, that problem will be described in detail with reference to the accompanying drawings.
Portion (a) of FIG. 6 is an enlarged cross-sectional view illustrating the structure of a portion of the known MISFET shown in FIG. 5 inside of the dotted line A. Portions (b) and (c) of FIG. 6 show the distributions of electric field intensities in the PN junction portion 30 and the MIS structure portion 40, which are indicated by the dotted line in portion (a) of FIG. 6, in the OFF state (i.e., when a drain voltage is applied). The pn junction portion 30 is formed of the body region 3 and the drift region 2d, while the MIS structure portion 40 is formed of the gate electrode 7, the gate insulating film 6 and the drift region 2d. 
When used as a power device, a MISFET is ideally designed so that breakdown occurs when the peak intensity of the electric field applied to the PN junction portion 30 exceeds the dielectric breakdown field of SiC (e.g., about 3 MV/cm for 4H—SiC). However, before the intensity of the electric field applied to the PN junction portion 30 reaches the dielectric breakdown field, the intensity of the electric field applied to the gate insulating film (of SiO2, for example) 6 could reach the dielectric breakdown field at the bottom of the trench. For that reason, breakdown could occur at a voltage that is lower than the theoretical breakdown voltage.
The reason is that as the difference in relative dielectric constant between SiC (e.g., 9.7 for 4H—SiC) and the SiO2 film (of 3.8) is smaller than the difference in relative dielectric constant between Si (of 11.9) and the SiO2 film (of 3.8), an electric field with a higher intensity is applied to the gate insulating film 6 of the MIS structure portion 40 in the SiC power device than in the Si power device. Also, in general, an electric field will be concentrated at respective portions of the gate insulating film 6 at the bottom and corners of the trench and a higher electric field will be applied to those portions than anywhere else. Furthermore, in the Si device, Si has a dielectric breakdown field of 0.2 MV/cm, which is two-digit smaller than 10 MV/cm of the SiO2 film. That is why in almost all cases, breakdown will occur in the PN junction portion of the Si device before breakdown occurs in the gate insulating film. In the SiC power device, on the other hand, SiC (4H—SiC) has as large a dielectric breakdown field as 3 MV/cm, which is much less different from that of the SiO2 film (e.g., about 0.5 to 1 digit). For that reason, the breakdown could occur in the MIS structure portion 40 due to the dielectric breakdown of the gate insulating film 6 before breakdown occurs in the PN junction portion 30. As a result, the dielectric breakdown of the gate insulating film 6 in the MIS structure portion 40 raises an even more serious problem. In this manner, the dielectric breakdown of the gate insulating film 6 could limit the dielectric withstanding voltage of the MISFET.
Thus, to overcome such a problem, Patent Document Nos. 1 and 2 propose that the dielectric breakdown field be increased by thickening the gate insulating film at the bottom of the trench.
Specifically, Patent Document No. 1 proposes making a portion of the gate insulating film (which is a thermal oxide film) at the bottom of the trench thicker than another portion of the gate insulating film on the side surface of the trench by using a (0001) carbon plane with a higher oxidation rate as the bottom of the trench. On the other hand, according to the method proposed in Patent Document No. 2, first of all, a gate insulating film, a polysilicon film and a silicon nitride film are deposited in this order inside of the trench. Next, the silicon nitride film is etched to expose the polysilicon film at the bottom of the trench. Subsequently, the exposed polysilicon film is oxidized to form a silicon dioxide film. Thereafter, the residual portions of the silicon nitride film and polysilicon film on the side surface of the trench are removed. In this manner, only the portion of the gate insulating film at the bottom of the trench can be thickened selectively.